1. Field of the Invention
This invention relates to an improved method and apparatus for transmitting digital data at high speeds via a parallel data bus, and more particularly, to a method and apparatus that provides a cost effective modular, high banded input/output element that can serve economically a few channels and is modularly scalable to serve several hundred channels.
2. Cross Reference to Related Applications
The present United States patent application is related to the following co-pending United States patent applications incorporated herein by reference:
Application Ser. No. 08/262,087, filed Jun. 17, 1994, now U.S. Pat. No. 5,487,095, entitled "Digital Phase Locked Loop with Improved Edge Detector," and assigned to the assignee of this application.
Application Ser. No. 08/261,515, filed Jun. 17, 1994, still pending entitled "Self-Timed Interface," and assigned to the assignee of this application.
Application Ser. No. 08/261,522, filed Jun. 17, 1994, still pending, entitled "Multiple Processor Link," and assigned to the assignee of this application.
Application Ser. No. 08/261,603, filed Jun. 17, 1994, still pending, entitled "Massively Parallel System," and assigned to the assignee of this application.
Application Ser. No. 08/261,523, filed Jun. 17, 1994, still pending, entitled "Attached Storage Media Link," and assigned to the assignee of this application.
Application Ser. No. 08/261,641, filed Jun. 17, 1994, still pending, entitled "Shared Channel Subsystem," and assigned to the assignee of this application.
3. Description of the Prior Art
As will be appreciated by those skilled in the art, such factors as noise and loading limit the useful length of parallel busses operating at high data rates. In the prior art, the length of the bus must be taken into account in the system design and the bus length must be precisely as specified. Manufacturing tolerances associated with physical communication link (chips, cables, cord wiring, connectors, etc.) and temperature and variations in power supply voltage also limit the data rates on prior art busses comprised of parallel conductors. Further, many prior art computer systems transfer data synchronously with respect to a processor clock, so that a change in processor clock rate may require a redesign of the data transfer bus.
General purpose computer systems are comprised of central processing element(s), local memory (storage) elements and input/output (I/O) elements. Of these, the processing and storage elements have benefitted directly from the continuous advances being made in circuit density, enabling more and more processing capability/storage per chip.
The I/O element, gated by other physical constraints, has not been able to track the performance gains of the processing/storage elements. Hence, the I/O element can limit the overall computer systems' performance in many applications. Further aggravating this problem are new system applications, such as client/server, that require large numbers of I/O, and multimedia that demand higher performance I/O elements. It also follows that for many applications, the smaller and smaller, yet faster, central processor elements (benefitting from circuit technology density advances) require more and more I/O capability to satisfy the increased demand for data (to be moved and/or to be processed). These trends can be expected to persist. Given that a primary role of a computer system I/O element is that of a transformer of bus speed (as well as of protocol and technology) between increasingly faster processor/storage elements and the slower, relatively unchanging speed of the attached I/O controllers, plus increases in required connectivity will continue to drive the need for improved efficiency and performance of the I/O element.
The I/O element often takes the form, especially on the most powerful systems, of a large multiplexer feeding and being fed by a network of more numerous and slower buses/links (becoming more numerous and slower the further away from the host they are in the network).
A current typical large computer system I/O element can require more than 100 channel functions as the middle stage/level in a hierarchically arranged busing network (between the highest level internal bus (fastest) and the more numerous and slower I/O controllers). The channel functions are packaged as part of the computer system and provide the interfaces to communicate, over distance (km), with the I/O controllers.
The large number of channel functions required, the channel transceiver design, the power required for distance and the connectors needed for external cable attachment all impede I/O element miniaturization.
In the prior art system, efforts are made in the I/O element design to avoid requiring excessive host signal pins (obtainable only through exotic/expensive packaging). Toward that end, minimum width data path/bus connections are employed between the channels and higher levels (internal buses) of the network. Even so, the number of signal pins, internal cables, connectors and circuit board complexity remains high.
The narrow buses are cycled faster than wider buses to achieve equivalent data transmission performance; however, this restricts maximum bus (cable) length. This trade-off between cable distance/net length and cycle time is typical with most prior art bus/link technologies and is a significant packaging constraint. Optimal packaging for cost and extendibility is compromised by requiring all channels to be within a limited (e.g., 3 meters) cable distance from the processor storage/control elements. This is especially troublesome in the more powerful systems where the system package must accommodate 100 or more channels.
Then too, prior art systems operate the numerous channels/buses synchronously to the host system clock to avoid inflating host circuit count via additional synchronizing buffers and logic. The channels/buses operating cycle time ranges are slower than the host, thus clock multiplier logic is used to provide clocks that are a multiple of the host clock cycle. This adds complexity to the design (as different multipliers can be required when host cycle times change) to remain within channel/bus operating ranges.